1. Field of the Invention
The present invention is directed to methods and systems for protecting integrated circuits (“ICs”) from power-on sequence currents and, more particularly, to methods and systems for biasing transistors in paths susceptible to power-on sequencing damage such that these paths do not have substantial current flow unless the power supplies controlling the gate of the susceptible transistors are powered on.
2. Background Art
Circuit boards commonly use multiple power supplies. When the power supplies are powered on at different times, undesired currents tend to flow between the power supplies. These undesired currents are referred to herein as power-on sequence currents. Power-on sequence currents can damage integrated circuits (“ICs”) on the circuit boards.
For example, core logic may be designed to operate at VDDC/VDDP (1.2V/1.5V/1.8V/2.5V) while an output driver may be required to operate at VDDP/VDDO (1.5V/1.8V/2.5V/3.3V). Voltage level shifting circuits are typically used to interface core signals to the output driver control signals. Voltage level shifting circuits may be designed to operate between two or more power supplies such as VDDO and VDDC. Gate-oxide portions of transistors in these level-shifting circuits may be able to withstand maximum of VDDO-VDDC across the gate-oxide portions.
When these ICs are put into system boards, the different power-supplies may be powered-on at different times. For instance, VDDO may be powered-on before VDDC. This can cause a voltage higher than VDDO-VDDC to appear across the gate-oxide of these transistors during the power-up, potentially damaging the gate-oxide.
Another situation that can cause problems is when I/O buffers require multiple level power supplies, such as 3.3V or 2.5V for example, to interface with other circuits. A number of different I/O buffer circuits may be designed on a chip. In such a design, I/O buffers are selected according to the input signal level or I/O supply voltage level. If the I/O pad voltage is powered up before the core supply voltage is powered up, the core supply voltage may not select a proper I/O buffer circuit. As a result, a higher I/O supply voltage may be inadvertently applied to thinner gate-oxide/shorter gate length I/O circuitry.
Problems similar to those described above can occur during transients and/or glitches on power supply lines.
Methods and systems are needed to protect circuits from over-voltage conditions across IC terminals during power-on sequences, and/or during transients and/or glitches on power supply lines during normal operations.